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For new designs, please refer to the PALCE22V10.
PALC22V10D Flash Erasable, Reprogrammable CMOS P AL
Features
R
Device
D
DIP LCC, and PLCC available , 7.5 ns commercial version 5 ns tCO 5 ns tS 7.5 ns tPD 133 MHz state machine 10 ns military and industrial ver sions 6 ns tCO 6 ns tS 10 ns tPD 110 MHz state machine 15 ns commercial and military versions 25 ns commercial and military versions
D
High reliability Proven Flash EPROM technology 100% programming and functional testing
D D D D D
Advanced second generation PAL ar chitecture Low power 90 mA max. commercial (10 ns) 130 mA max. commercial (7.5 ns) CMOS Flash EPROM technology for electrical erasability and reprogram mability Variable product terms 2 x (8 through 16) product terms User programmable macrocell Output polarity control Individually selectable for regis tered or combinatorial operation
Functional Description
The Cypress P ALC22V10D is a CMOS Flash Erasable second generation pro
grammable array logic device. It is im plemented with the familiar sum of pro ducts (AND OR) logic structure and the programmable macrocell. The P ALC22V10D is executed in a 24 pin 300 mil molded DIP a 300 mil cerDIP a , , 28 lead square ceramic leadless chip carri er, a 28 lead square plastic leaded chip car rier, and provides up to 22 inputs and 10 outputs. The 22V10D can be electrically
D
Up to 22 input terms and 10 outputs
Logic Block Diagram (PDIP/CDIP)
VSS 12 I 11 I 10 I 9 I 8 I 7 I 6 I 5 I 4 I 3 I 2 CP/I 1
PROGRAMMABLE AND ARRAY (132 X 44) 8 10 12 14 16 16 14 12 10 8
Reset
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Preset
13 I
14 I/O9
15 I/O8
16 I/O 7
17 I/O6
18 I/O5
19 I/O4
20 I/O3
21 I/O2
22 I/O1
23 I/O0
24 V CC V10D 1
Pin Configuration
LCC Top View VCC CP/I 0 I/O 1 PLCC Top View CP/I 0 I/O I/O 1 V CC NC 1
NC
I/O
I 4 I/O 2 I/O 3 I/O 4 N/C I/O 5 I/O 6 I/O 7 V10D 2 I I I NC I I I 5 6 7 8 9 10 11
I
I
4 I I I NC I I I 5 6 7 8 9 10 11
321
28 27 26 25 24 23 22 21 20 19
3
I
2
28 27 26 25 24 23 22 21 20 19 I/O 2 I/O 3 I/O 4 N/C I/O 5 I/O 6 I/O 7
12 13 14 15 16 17 18 NC I/O9 I/O8 V SS I I I
12 13 14 15 16 17 18
NC
I/O9
P AL is a registered trademark of Advanced Micro Devices.
Cypress Semiconductor Corporation
D
3901 North First Street 1
D
San Jose
D
I/O8
V SS
V10D 3
I
I
I
CA 95134
D
408-943-2600
July 1991 - Revised October 1995
PALC22V10D
Functional Description
(continued)
erased and reprogrammed. The programmable macrocell provides the capability of defining the architecture of each output individu ally. Each of the 10 potential outputs may be specified as regis tered" or combinatorial." Polarity of each output may also be in dividually selected, allowing complete flexibility of output configuration. Further configurability is provided through array" configurable output enable" for each potential output. This fea ture allows the 10 outputs to be reconfigured as inputs on an indi vidual basis, or alternately used as a combination I/O controlled by the programmable array. PALC22V10D features a variable product term architecture. There are 5 pairs of product term sums beginning at 8 product terms per output and incrementing by 2 to 16 product terms per output. By providing this variable structure, the PAL C 22V10D is optimized to the configurations found in a majority of applications without creating devices that burden the product term structures with unusable product terms and lower performance. Additional features of the Cypress PALC22V10D include a syn chronous preset and an asynchronous reset product term. These product terms are common to all macrocells, eliminating the need to dedicate standard product terms for initialization functions. The device automatically resets upon power up. The PALC22V10D, featuring programmable macrocells and vari able product terms, provides a device with the flexibility to imple ment logic functions in the 500 to 800 gate array complexity. Since each of the 10 output pins may be individually configured as inputs on a temporary or permanent basis, functions requiring up to 21 inputs and only a single output and down to 12 inputs and 10 outputs are possible. The 10 potential outputs are enabled using
Macrocell
product terms. Any output pin may be permanently selected as an output or arbitrarily enabled as an output and an input through the selective use of individual product terms associated with each out put. Each of these outputs is achieved through an individual pro grammable macrocell. These macrocells are programmable to pro vide a combinatorial or registered inverting or non inverting output. In a registered mode of operation, the output of the regis ter is fed back into the array, providing current status information to the array. This information is available for establishing the next result in applications such as control state machines. In a combina torial configuration, the combinatorial output or, if the output is disabled, the signal present on the I/O pin is made available to the array. The flexibility provided by both programmable product term control of the outputs and variable product terms allows a signifi cant gain in functional density through the use of programmable logic. Along with this increase in functional density, the Cypress PALC22V10D provides lower power operation through the use of CMOS technology, and increased testability with Flash repro grammability.
Configuration Table
Registered/Combinatorial C1 C0 Configuration
0 0 1 1
0 1 0 1
Registered/Active LOW Registered/Active HIGH Combinatorial/Active LOW Combinatorial/Active HIGH
AR
OUTPUT SELECT D Q MUX
CP
Q
S1
S0
SP
INPUT/ FEEDBACK MUX S1
C1 C0 MACROCELL
V10D 4
2
PALC22V10D
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature . . . . . . . . . . . . . . . . . . -65_C to +150_C Ambient Temperature with Power Applied . . . . . . . . . . . . . . . . . . . . . . . -55_C to +125_C Supply Voltage to Ground Potential (Pin 24 to Pin 12) . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7.0V DC Voltage Applied to Outputs in High Z State . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7.0V DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7.0V Output Current into Outputs (LOW) . . . . . . . . . . . . . . 16 mA DC Programming Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 12.5V Latch Up Current . . . . . . . . . . . . . . . . . . . . . . . . . . . >200 mA
Electrical Characteristics
Parameter
Static Discharge Voltage (per MIL-STD-883, Method 3015) . . . . . . . . . . . . . . >2001V
Operating Range
Ambient Range Temperature VCC
Commercial Military[1] Industrial
0_C to +75_C -55_C to +125_C -40_C to +85_C
5V 5% 5V 10% 5V 10%
Over the Operating Range[2]
Test Conditions Min. Max. Unit
Description
VOH VOL VIH VIL[4] IIX IOZ ISC ICC1
Output HIGH Voltage
VCC = Min., VIN = VIH or VIL VCC = Min., VIN = VIH or VIL
IOH = -3.2 mA IOH = -2 mA IOL = 16 mA IOL = 12 mA
Com'l Mil/Ind Com'l Mil/Ind
2.4
V
Output LOW Voltage
0.5
V
Input HIGH Level Input LOW Level Input Leakage Current Output Leakage Current Output Short Circuit Current Standby Power Supply Current
Guaranteed Input Logical HIGH Voltage for All Inputs[3] Guaranteed Input Logical LOW Voltage for All Inputs[3] VSS < VIN < VCC, VCC = Max. VCC = Max., VSS < VOUT < VCC VCC = Max., VOUT = 0.5V[5, 6] Com'l VCC = Max., 10, 15, 25 ns VIN = GND GND, p p Outputs Open in 7.5 ns Unprogrammed 15, 25 ns Device 10 ns VCC = Max., VIL = 0V, 0V VIH = 3V, 3V p p, Output Open, De vice Programmed as a 10 Bit Counter, MHz f = 25 MH 10, 15, 25 ns 7.5 ns 15, 25 ns 10 ns Mil/Ind
2.0 -0.5 -10 -40 -30 0.8 10 40 -90 90 130
V V
mA mA
mA mA mA mA mA mA mA mA mA
Mil/Ind
120 120
ICC2[6]
Operating Power Supply Current
Com'l
110 140 130 130
Capacitance
Parameter
[6]
Description Test Conditions Min. Max. Unit
CIN COUT
Input Capacitance Output Capacitance
[6]
VIN = 2.0V @ f = 1 MHz VOUT = 2.0V @ f = 1 MHz
10 10
pF pF
Endurance Characteristics
Parameter
Description
Test Conditions
Min.
Max.
Unit
N
1. 2. 3. 4.
Notes:
Minimum Reprogramming Cycles
Normal Programming Conditions
5. 6.
100
Cycles
TA is the instant on" case temperature. See the last page of this specification for Group A subgroup testing in formation. These are absolute values with respect to device ground. All over shoots due to system or tester noise are included. VIL (Min.) is equal to -3.0V for pulse durations less than 20 ns.
Not more than one output should be tested at a time. Duration of the short circuit should not be more than one second. VOUT = 0.5V has been cho sen to avoid test problems caused by tester ground degradation. Tested initially and after any design or process changes that may affect these parameters.
3
PALC22V10D
AC Test Loads and Waveforms
R1 238W (319W MIL) 5V OUTPUT R2 170W CL INCLUDING JIG AND SCOPE (236W MIL) INCLUDING JIG AND SCOPE 5 pF 5V OUTPUT R2 170W (236W MIL) CL OUTPUT R1 238W (319W MIL)
750W (1.2KW MIL)
(a)
(b)
(c)
ALL INPUT PULSES 3.0V 90% 10% GND < 2 ns < 2 ns 90% 10%
(d)
Equivalent to: THEVENIN EQUIVALENT (Commercial) 99W OUTPUT 2.08V = Vthc
V10D 6
V10D 5
Equivalent to:
THEVENIN EQUIVALENT (Military) 136W
OUTPUT
2.13V = Vthm
V10D 7
Load Speed
CL
Package
Parameter
VX
Output Waveform
Measurement Level
7.5, 10, 15, 25 ns
50 pF
PDIP CDIP , , PLCC, LCC
tER (-) tER (+) tEA (+) tEA (-)
1.5V
VOH
0.5V 0.5V
VX VX
V10D 8
2.6V
VOL
V10D 9
0V
VX VX
1.5V
VOH
V10D 10
Vthc
0.5V
(e) Test Waveforms
VOL
V10D 11
4
PALC22V10D
Commercial Switching Characteristics PALC22V10D
Parameter
tPD tEA tER tCO tS1 tS2 tH tP tWH tWL fMAX1 fMAX2 fMAX3 tCF tAW tAR tAP tSPR
[2, 7]
Description
Input to Output Propagation Delay[8, 9] Input to Output Enable Delay[10] Input to Output Disable Delay[11] Clock to Output Delay[8, 9] Input or Feedback Set Up Time Synchronous Preset Set Up Time Input Hold Time External Clock Period (tCO + tS) Clock Width HIGH Clock Width LOW
[6]
22V10D-7 Min. Max.
3 7.5 8 8 2 5 6 0 10 3 3 100 166 133 2.5 8 5 12 6 1 5
22V10D-10 Min. Max.
3 10 10 10 2 6 7 0 12 3 3 76.9 142 111 3 10 6 13 8 1 7
22V10D-15 Min. Max.
3 15 15 15 2 10 10 0 20 6 6 55.5 83.3 68.9 4.5 15 10 20 10 1 8
22V10D-25 Min. Max.
3 25 25 25 2 15 15 0 30 13 13 33.3 35.7 38.5 13 25 25 25 15 1 15
Unit
ns ns ns ns ns ns ns ns ns ns MHz MHz MHz ns ns ns ns ns
[6]
External Maximum Frequency (1/(tCO + tS))[12] Data Path Maximum Frequency (1/(tWH + tWL))[6, 13] Internal Feedback Maximum Frequency (1/(tCF + tS))[6, 14] Register Clock to Feedback Input[6, 15] Asynchronous Reset Width Asynchronous Reset Recovery Time Asynchronous Reset to Registered Output Delay Synchronous Preset Recovery Time Power Up Reset Time
[6, 16]
Notes:
7. 8. 9.
tPR
ms
Part (a) of AC Test Loads and Waveforms is used for all parameters ex cept tER and tEA(+). Part (b) of AC Test Loads and Waveforms is used for tER. Part (c) of AC Test Loads and Waveforms is used for tEA(+). Min. times are tested initially and after any design or process changes that may affect these parameters. This specification is guaranteed for all device outputs changing state in a given access cycle.
12. This specification indicates the guaranteed maximum frequency at which a state machine configuration with external feedback can operate. 13. This specification indicates the guaranteed maximum frequency at which the device can operate in data path mode. 14. This specification indicates the guaranteed maximum frequency at which a state machine configuration with internal only feedback can operate. 15. This parameter is calculated from the clock period at fMAX internal (1/fMAX3) as measured (see Note 11 above) minus tS. 16. The registers in the PALC22V10D have been designed with the capa bility to reset during system power up. Following power up, all regis ters will be reset to a logic LOW state. The output state will depend on the polarity of the output buffer. This feature is useful in establishing state machine initialization. To insure proper operation, the rise in VCC must be monotonic and the timing constraints depicted in Power Up Reset Waveform must be satisfied.
10. The test load of part (a) of AC Test Loads and Waveforms is used for measuring tEA(-). The test load of part (c) of AC Test Loads and Waveforms is used for measuring tEA(+) only. Please see part (e) of AC Test Loads and Waveforms for enable and disable test waveforms and measurement reference levels. 11. This parameter is measured as the time after output disable input that the previous output data state remains stable on the output. This delay is measured to the point at which a previous HIGH level has fallen to 0.5 volts below VOH min. or a previous LOW level has risen to 0.5 volts above VOL max. Please see part (e) of AC Test Loads and Waveforms for enable and disable test waveforms and measurement reference levels.
5
PALC22V10D
Military and Industrial Switching Characteristics PALC22V10D
Parameter
tPD tEA tER tCO tS1 tS2 tH tP tWH tWL fMAX1 fMAX2 fMAX3 tCF tAW tAR tAP tSPR tPR
[2, 7]
Description
Input to Output Propagation Delay[8, 9] Input to Output Enable Delay[10] Input to Output Disable Delay[11] Clock to Output Delay[8, 9] Input or Feedback Set Up Time Synchronous Preset Set Up Time Input Hold Time External Clock Period (tCO + tS) Clock Width HIGH Clock Width LOW
[6]
22V10D-10 Min. Max.
3 10 10 10 2 6 7 0 12 3 3 76.9 142 111 3 10 6 12 8 1 7
22V10D-15 Min. Max.
3 15 15 15 2 10 10 0 20 6 6 50.0 83.3 68.9 4.5 15 12 20 20 1 8
22V10D-25 Min. Max.
3 25 25 25 2 18 18 0 33 14 14 30.3 35.7 32.2 13 25 25 25 25 1 15
Unit
ns ns ns ns ns ns ns ns ns ns MHz MHz MHz ns ns ns ns ns
[6]
External Maximum Frequency (1/(tCO + tS))[12] Data Path Maximum Frequency (1/(tWH + tWL))[6, 13] Internal Feedback Maximum Frequency (1/(tCF + tS))[6, 14] Register Clock to Feedback Input[6, 15] Asynchronous Reset Width Asynchronous Reset Recovery Time Asynchronous Reset to Registered Output Delay Synchronous Preset Recovery Time Power Up Reset Time[6, 16]
ms
6
PALC22V10D
Switching Waveform
INPUTS I/O, REGISTERED FEEDBACK SYNCHRONOUS PRESET tS tH t WH t WL
CP
t SPR t AW ASYNCHRONOUS RESET t CO t AP
tP t AR
tER
[11]
tEA
[11]
REGISTERED OUTPUTS t PD COMBINATORIAL OUTPUTS tER
[11]
tEA
[11]
V10D 12
Power Up Reset Waveform[16]
POWER SUPPLY VOLTAGE t PR REGISTERED ACTIVE LOW OUTPUTS tS 10% 90% VCC
CLOCK
tPR MAX = 1
ms
t WL
V10D 13
7
PALC22V10D
Functional Logic Diagram for PALC22V10D
1
AR OE 0 S S S 7 OE 0 0 4 8 12 16 20 24 28 32 36 40
Macro cell
23
S S S
2
9 OE 0
Macro cell
22
S S S
Macro cell
21
3
11 OE 0
S S S
Macro cell
20
4
13 OE 0
S S S
15 OE 0
Macro cell
19
5
S S S
15 OE 0
Macro cell
18
6
S S S
Macro cell
17
7
13 OE 0
S S S
Macro cell
16
8
11 OE 0
S S S
Macro cell
15
9
9 OE 0 S S S 7 SP V10D 14
10 11
Macro cell
14 13
8
PALC22V10D
Ordering Information
ICC (mA) tPD (ns) tS (ns) tCO (ns) Ordering Code Package Name Package Type Operating Range
130 90 150 150 90 120 120 90 120 120
7.5 10 10 10 15 15 15 25 25 25
5 6 6 6
5 7 7 7
7.5 7.5 7.5 15 15 15
10 10 10 15 15 15
PALC22V10D-7JC PALC22V10D-7PC PALC22V10D-10JC PALC22V10D-10PC PALC22V10D-10JI PALC22V10D-10PI PALC22V10D-10DMB PALC22V10D-10KMB PALC22V10D-10LMB PALC22V10D-15JC PALC22V10D-15PC PALC22V10D-15JI PALC22V10D-15PI PALC22V10D-15DMB PALC22V10D-15KMB PALC22V10D-15LMB PALC22V10D-25JC PALC22V10D-25PC PALC22V10D-25JI PALC22V10D-25PI PALC22V10D-25DMB PALC22V10D-25KMB PALC22V10D-25LMB
J64 P13 J64 P13 J64 P13 D14 K73 L64 J64 P13 J64 P13 D14 K73 L64 J64 P13 J64 P13 D14 K73 L64
28 Lead Plastic Leaded Chip Carrier 24 Lead (300 Mil) Molded DIP 28 Lead Plastic Leaded Chip Carrier 24 Lead (300 Mil) Molded DIP 28 Lead Plastic Leaded Chip Carrier 24 Lead (300 Mil) Molded DIP 24 Lead (300 Mil) CerDIP 24 Lead Rectangular Cerpack 28 Square Leadless Chip Carrier 28 Lead Plastic Leaded Chip Carrier 24 Lead (300 Mil) Molded DIP 28 Lead Plastic Leaded Chip Carrier 24 Lead (300 Mil) Molded DIP 24 Lead (300 Mil) CerDIP 24 Lead Rectangular Cerpack 28 Square Leadless Chip Carrier 28 Lead Plastic Leaded Chip Carrier 24 Lead (300 Mil) Molded DIP 28 Lead Plastic Leaded Chip Carrier 24 Lead (300 Mil) Molded DIP 24 Lead (300 Mil) CerDIP 24 Lead Rectangular Cerpack 28 Square Leadless Chip Carrier
Commercial Commercial Industrial Military Commercial Industrial Military Commercial Industrial Military
MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics
VOH VOL VIH VIL IIX IOZ ICC
Parameter
1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3
Subgroups
Switching Characteristics
Parameter Subgroups
tPD 9, 10, 11 tCO 9, 10, 11 tS 9, 10, 11 tH 9, 10, 11 Document #: 38-00185-H 9
PALC22V10D
Package Diagrams
24 Lead (300 Mil) CerDIP D14
MIL-STD-1835 D-9 Config. A
28 Lead Plastic Leaded Chip Carrier J64
24 Lead Rectangular Cerpack K73
MIL-STD-1835 F-6 Config. A
28 Square Leadless Chip Carrier L64
MIL-STD-1835 C-4
10
PALC22V10D
Package Diagrams (continued)
24 Lead (300 Mil) Molded DIP P13/P13A
E
Cypress Semiconductor Corporation, 1995. The information contained herein is subject to change without notice.
Cypress Semiconductor Corporation assumes no responsibility for
the use of any circuitry other than circuitry embodied in a Cypress Semiconductor Corporation product. Nor does it convey or imply any license under patent or other rights. Cypress Semicon ductor does not authorize its products for use as critical components in life support systems where a malfunction or failure of the product may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life support systems applications implies that the manufacturer assumes all risk of such use and in so doing indemnifies Cypress Semiconductor against all damages.
11

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